Smart Interconnect: The Next Key Driver of HPC Performance Gains




The latest revolution in high-performance computing (HPC) is the move to a co-design architecture, a collaborative effort among industry thought leaders, academia, and manufacturers to reach exascale performance by taking a holistic system-level approach to fundamental performance improvements. Co-design architecture exploits system efficiency and optimizes performance by creating synergies between the hardware and the software, and between the different hardware elements within the data center.

Co-design recognizes that the CPU has reached the limits of its scalability, and offers an intelligent network as the new “co-processor” to share the responsibility for handling and accelerating application workloads. By placing data-related algorithms on an intelligent network, we can dramatically improve the data center and applications performance.

This webinar, presented by Mellanox, IDC and Oak Ridge National Laboratory, will examine the emerging technology of smart interconnects that are well positioned to address the performance bottlenecks of today HPC infrastructures. It will also look at the role that Mellanox is playing in defining and developing innovative solutions with its smart interconnects products for the new co-design architecture.

Presenters

Gilad Shainer
Vice President Marketing Mellanox Technologies


Bob Sorensen,
Research Vice President, High Performance Computing group, IDC


Scott Atchley,
Lead System Architecture, Resilience, and Networking, Oak Ridge National Laboratory

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